Conventional memory systems typically consist of one or more memory devices, such as dynamic random access memories (e.g. DRAMs), mounted on a Printed Circuit Board (PCB) called a Dual In-line Memory Module (DIMM). The memory system is in communication with a memory controller (MC) which in turn is in communication with a processor subsystem or central processing unit (CPU) or microprocessor. In some configurations, the memory controller is physically subsumed into the same physical chip as the processor. And in other configurations the memory controller may be just one of many logical components comprising a memory controller hub (MCH). A memory controller hub typically supports completely separate and distinct memory address spaces, often using different types of semiconductor memory for different purposes. For example, a memory controller may support the use of video DRAM for graphics applications, flash memory for disk-drive acceleration, and commodity DRAM as the processor's main external memory.
The limitations imposed by memory protocols, traditional memory subsystem architectures, standards, processor-specific memory access models, end-user configurability requirements, power constraints, or combinations of those limitations tend to interact in such a manner that reduce performance and result in non-optimal memory subsystems.
The disclosures herein describe methods and apparatus for improving memory subsystems by abstracting various properties of the memory subsystem and their components. The principles developed herein apply to embodiments of abstracted memories and abstracted DIMMs.